1. Field of the Invention
This invention relates to a method of dry etching in semiconductor processing and more particularly to an etch-back method of different silicon oxide layers to achieve topographical planarization.
2. Description of Related Art
The achievement of topographical planarization is important in forming semiconductor wafers that have two or more metal layers. In the usual case, a semiconductor structure is produced comprising layers of oxide, polysilicon, and first metal wiring, or conductors, covered with an intermediate insulator layer. The surface of this latter layer is irregular with sharp edges and cracks. To apply a second layer of metal such as aluminum, on its surface is not practical because it will result in cracks or separations in the metal, or incomplete metal coverage, so that device yield would be significantly reduced. Thus, it is necessary to provide a method for planarizing the insulator layer to provide a smoother surface topography for application of a second or subsequent metal layer.
FIG. 1 illustrates a conventional method for providing topographical planarization of silicon oxide layers, in particular, intermediate insulator layers, which is in common practice. As shown in FIG. 1, metal wiring or conductors 2, e.g., Al, are formed by vapor deposition of a metal layer on substrate 1 followed by selective etching of the metal layer to form conductors 2. Then, oxide layer 3, i.e., SiO.sub.2 layer, is formed by CVD followed by formation through thermal oxidation of SOG layer 4 which fills the gaps and indentations formed by first oxide layer 3 over conductors 2. As illustrated in FIG. 1, the surface of SOG layer 4 is irregular. The present practice is to subject the combination layers 3 and 4 to a dry or plasma etch-back process by sputtering or ion milling to reduce the thickness of these layers to the level indicated by dotted line 5, so that an enhanced planarized surface and contour is achieved. The process employed is a physical etching procedure wherein ion milling of the insulator film surfaces is accomplished in a reactive ion etching system employing an inert gas, such as, Ar. The selectivity of the second silicon oxide layer 4 (SOG) with respect to the first silicon layer 3 (SiO.sub.2) is about 1.18. The etch-back process chosen should be selected to closely match as best as possible the etch rate for SOG layer 4 and SiO.sub.2 layer 3. Ideally, such a selectivity ratio should be 1.0:1.0 but this is, in practice, not generally possible. In any case, a selectivity ratio in the range of 0.8-1.7:1.0 is acceptable. Further, the thicker SOG layer 4 is, the more planarized is the surface that can be achieved, but accompanied with a correspondingly longer period of time required for the etch-back process.
The employment of ion milling methods utilizing heavy inert Ar ions to impact the surface of layers 3,4, physically remove molecular materials from the surface. The etching rates achieved are relatively low, for example, several tens of nanometers per minute so that the etch-back process can be comparatively quite long. This process can be so long in the case of a thick SOG layer 4, that it becomes impractical.
Further, the employment of ion milling or other such physical etching method results in damage to the semiconductor structure due to the physical ion bombardment. The resulting effect is an increase in threshold voltages for subsequently formed transistors.
Also, the SiO.sub.2 molecules removed from the surface adhere to the plasma system electrode, resulting in the re-adherence of SiO.sub.2 particles on the surface being etched, and in lower device yield. This particular problem becomes more pronounced as SOG layer 4 is deposited with increasing thickness.
It is also known to use a plasma etch comprising fluorocarbon gases wherein a primary etching gas, such as, C.sub.2 F.sub.6, is employed in combination with a secondary gas, such as, CHF.sub.3 or O.sub.2, to control the selectivity of the etch. Such a system provides for a chemical etching rather than a physical etching to etch-back silicon oxide. Also, an inert gas may be employed as a carrier gas. These plasmas contain active fluorine species and the addition of O.sub.2 enhances the effectiveness of the plasma because O.sub.2 helps to inhibit the recombination between fluoride radicals, F*, and thereby increases and extends their concentration. The inert gas, such as, helium or argon, employed in these etching environments as a carrier gas helps to control the temperature during the etching process. See, for example U.S. Pat. No. 4,676,867. However, the continuing problem with these fluorocarbon etching systems is the lack of repeatable control over the rate and uniformity of etching. It is very difficult to etch different types of SiO.sub.2 films, e.g., TEOS, by means of chemical etching. In particular, such chemical etching of a SOG layer is generally about 3 to 5 times higher than a thermal oxide layer. However, in the manufacturing step utilizing the etch-back of a combination of these oxide layers, it is necessary that the etching rate of both such layers be approximately the same, i.e., as close as possible to a selectivity ratio of 1.0/1.0.
Thus, what is needed is a better means of controlling the rate of chemical etching when employing a fluorocarbon reactive ion etching system wherein the rate of etching can be controlled in a practical, repeatable manner achieving optimized selectivity.
Thus, it is an object of this invention to provide a method of dry etching having a high etching rate with a relatively low selectivity ratio providing for a reduced etching time with high reliability and repeatability to provide a corresponding improved yield rate in the production of semiconductor devices.
It is another object of this invention to provide a method of applying an absorption layer to an etching surface to provide a buffering effect to highly active etching medium.
It is another object of this invention to provide an etching system having a predetermined gap width between spatially parallel electrodes of the etching system to provide for optimum etching uniformity.
It is another object of this invention to provide a method of uniform planarization relative to first and second oxide layers deposited on a semiconductor wafer through the use of a dry etching medium comprising first and second etchback steps wherein one step has a selectivity greater than one and the other step has a selectivity less than one.